提问


参考开发板提供的 《 多端口以太网应用.zip 》,将其中使用 GMAC 的四路网口删除,使用

使能ZYNQ片上MAC1,按照文档《AX7021_FL9031多以太网应用.pdf》,修改LWIP库,使用

SDK测试ETH0发现,测试正常

测试ETH1, 仅仅将SDK头文件修改为

#define PLATFORM_EMAC_BASEADDR XPAR_PS7_ETHERNET_1_BASEADDR

却发现ETH1总是ping不通

ETH0和ETH1的串口打印都一样如下所示:

-----lwIP TCP echo server ------
TCP packets sent to port 6001 will be echoed back
WARNING: Not a Marvell or TI Ethernet PHY. Please verify the initialization sequence
Start PHY autonegotiation_ksz9031
Waiting for PHY to complete autonegotiation.
autonegotiation complete_ksz9031
link speed for phy address 1: 1000
DHCP Timeout
Configuring default IP of 192.168.1.10
Board IP: 192.168.1.10
Netmask : 255.255.255.0
Gateway : 192.168.1.1
TCP echo server started @ port 7

ETH0能够ping通 192.168.1.10

ETH1却不可以

附件加上工程,请黑金的工程师帮忙解决一下问题,因为项目需求只需要双网卡,

并且FPGA资源紧张,不能使用赛灵思的 GMAC,请黑金的同事找找问题,相信也有很多我这样的困扰的用法。多谢!!!




回答
  • 171049129@qq.com

    2020-10-19


    补充:FCLK_CLK1设置为200Mhz

    0
  • 171049129@qq.com

    2020-10-19


    工程打包上传失败,这里截图贴出来关键信息,GMII TO RGMII的设置如上图,其中GPIO_0_0是给 ksz9031(PHY1)的复位

    信号,在xdc文件中做了上拉处理。

    # ETH1
    set_property PACKAGE_PIN J17 [get_ports {MDIO_PHY_0_mdc }]
    set_property PACKAGE_PIN J16 [get_ports {MDIO_PHY_0_mdio_io }]
    #set_property PACKAGE_PIN M20 [get_ports {MDIO_PHY_0_mdc }]
    #set_property PACKAGE_PIN T17 [get_ports {MDIO_PHY_0_mdio_io }]
    set_property IOSTANDARD LVCMOS33 [get_ports {MDIO_PHY_0_mdc }]
    set_property IOSTANDARD LVCMOS33 [get_ports {MDIO_PHY_0_mdio_io }]

    set_property PACKAGE_PIN K19 [get_ports {RGMII_0_rxc }]
    set_property PACKAGE_PIN K20 [get_ports {RGMII_0_rx_ctl }]
    set_property PACKAGE_PIN R21 [get_ports {RGMII_0_txc }]
    set_property PACKAGE_PIN R20 [get_ports {RGMII_0_tx_ctl }]
    #set_property PACKAGE_PIN M19 [get_ports {RGMII_0_rxc }]
    #set_property PACKAGE_PIN P17 [get_ports {RGMII_0_rx_ctl }]
    #set_property PACKAGE_PIN K16 [get_ports {RGMII_0_txc }]
    #set_property PACKAGE_PIN M22 [get_ports {RGMII_0_tx_ctl }]
    set_property IOSTANDARD LVCMOS33 [get_ports {RGMII_0_rxc }]
    set_property IOSTANDARD LVCMOS33 [get_ports {RGMII_0_rx_ctl }]
    set_property IOSTANDARD LVCMOS33 [get_ports {RGMII_0_txc }]
    set_property IOSTANDARD LVCMOS33 [get_ports {RGMII_0_tx_ctl }]
    create_clock -period 5.000 -name clkin -add [get_nets clkin]
    create_clock -period 8.000 -name RGMII_0_rxc [get_ports RGMII_0_rxc]
    #create_clock -period 8.000 -name RGMII_0_txc [get_ports RGMII_0_txc]

    set_property PACKAGE_PIN J18 [get_ports {RGMII_0_rd[0] }]
    set_property PACKAGE_PIN K18 [get_ports {RGMII_0_rd[1] }]
    set_property PACKAGE_PIN J15 [get_ports {RGMII_0_rd[2] }]
    set_property PACKAGE_PIN K15 [get_ports {RGMII_0_rd[3] }]
    set_property PACKAGE_PIN N17 [get_ports {RGMII_0_td[0] }]
    set_property PACKAGE_PIN N18 [get_ports {RGMII_0_td[1] }]
    set_property PACKAGE_PIN N19 [get_ports {RGMII_0_td[2] }]
    set_property PACKAGE_PIN N20 [get_ports {RGMII_0_td[3] }]

    #set_property PACKAGE_PIN P18 [get_ports {RGMII_0_rd[0] }]
    #set_property PACKAGE_PIN P22 [get_ports {RGMII_0_rd[1] }]
    #set_property PACKAGE_PIN N22 [get_ports {RGMII_0_rd[2] }]
    #set_property PACKAGE_PIN M21 [get_ports {RGMII_0_rd[3] }]
    #set_property PACKAGE_PIN L18 [get_ports {RGMII_0_td[0] }]
    #set_property PACKAGE_PIN L22 [get_ports {RGMII_0_td[1] }]
    #set_property PACKAGE_PIN L21 [get_ports {RGMII_0_td[2] }]
    #set_property PACKAGE_PIN L16 [get_ports {RGMII_0_td[3] }]
    set_property IOSTANDARD LVCMOS33 [get_ports {RGMII_0_rd[0] }]
    set_property IOSTANDARD LVCMOS33 [get_ports {RGMII_0_rd[1] }]
    set_property IOSTANDARD LVCMOS33 [get_ports {RGMII_0_rd[2] }]
    set_property IOSTANDARD LVCMOS33 [get_ports {RGMII_0_rd[3] }]
    set_property IOSTANDARD LVCMOS33 [get_ports {RGMII_0_td[0] }]
    set_property IOSTANDARD LVCMOS33 [get_ports {RGMII_0_td[1] }]
    set_property IOSTANDARD LVCMOS33 [get_ports {RGMII_0_td[2] }]
    set_property IOSTANDARD LVCMOS33 [get_ports {RGMII_0_td[3] }]

    set_property PACKAGE_PIN L19 [get_ports {GPIO_0_0_tri_io }]
    set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_0_0_tri_io }]
    set_property PULLUP true [get_ports GPIO_0_0_tri_io]

    0

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